22nd IEEE Latin-American Test Symposium

Virtual Symposium, 27th - 29th October 2021




Talks & Speakers


Here are some more details on this year's talks.

We are proud to have gathered a broad spectrum of topics presented by speakers from research and industry.




October 27th, 2021 (Wednesday)



10:30 – 11:10 (GMT-3, Brazil): Invited Talk

Hardware Security and Machine Learning: Hero or Hoax?

Prof. Giorgio di Natale, Université Grenoble Alpes (France)

Session Chair: TBD


Abstract: In the last two decades we have witnessed a massive development of technologies (both hardware and software) which have enabled the creation of billions of connected devices. These devices are nowadays used in a very wide range of applications, and they all contain different types of valuable assets, which have been the target of an increasing number of cyber attacks. Both scientific and industrial communities have focused their attention to implement new design processes to reduce the risk of cybersecurity breaches. Among the novel techniques used to enhance the security of such devices, Machine Learning (ML) has emerged as one of the most promising. This talk will explore the wide range of security solutions based on ML, by highlighting their advantages and drawbacks.



16:00 – 16:45 (GMT-3, Brazil): Visionary Talk

Prof. Krishnendu Chakrabarty, Duke University (USA)

Session Chair: TBD


Abstract: The ubiquitous application of deep neural networks (DNN) has led to a rise in demand for AI accelerators. DNN-specific functional criticality analysis identifies faults that cause measurable and significant deviations from acceptable requirements, e.g.,  inferencing accuracy. This talk will examine the problem of classifying structural faults in neural networks based on three promising hardware architectures: (a) systolic-array accelerator, (b) resistive random-access memory (ReRAM)-based systems, and (iii) silicon photonics neural networks. The impact of hardware faults and variations in these three types of systems will analyzed, and techniques will be presented to assess the functional criticality of faults and variations.





October 28th, 2021 (Thursday)



10:00 - 10:40 (GMT-3, Brazil): Invited Talk 2

Analyzing Data Extracted from Radiation Tests in Advanced SRAMs

Prof. Juan Antonio Clemente Barreira, UCM (Spain)

Session Chair: TBD


Abstract: When researchers perform experiments on advanced SRAMs in order to assess their sensitivity against radiation, it is important to correctly classify the observed errors according to their multiplicity (Single Bit Upsets (SBUs), Multiple Cell Upsets (MCUs), etc). However, this might become a challenge in modern devices that implement mechanisms to detect and correct such errors (bit interleaving and Error Correcting Codes (ECC), amongst others). The reason is that this information is usually intellectual property (IP) of the manufacturers. In this talk we will discuss how this problem can be solved, even if said proprietary information is unknown to researchers. In addition, we will discuss the impact of error accumulation in experiments where too many bitflips are observed (due to a high particle flux, for example), and why the probability of observed so-called "false multiple events" is not negligible."



11:40 – 12:20 (GMT-3, Brazil): Industry Talk 1

How to Feed a Growing Population while Conserving the Planet's Resources – IoT to the Rescue

Dr. Victor Grimblatt, Synopsys (Chile)

Session Chair: TBD


Abstract: World population is growing and according to FAO (United Nations Food and Agriculture Organization) the agriculture production should increase by 70% by 2050. On the other hand it is also well known that the agriculture is dramatically impacting the 9 planetary boundaries defined by Johan Rockström and his group in 2009. So we are facing a big dilemma, how to improve the productivity of the soil without impacting the planet and its limits. The growth of crops depend on several parameters such as soil moisture, soil temperature, nutrients (fertilizers), soil pH, soil salinity, etc. Without having an on line measurement (real time) of those parameters we will probably be able to get products from the ground, however we are not taking in account what are the impact of what we are doing and the way we are making agriculture. With the appropriate sensors and IoT we are able not only to know the level of the parameters already mentioned but also to act based on the results. This talk will present an IoT approach to measure relevant parameters for crop growth and health while keeping the planet safe. It will also cover the need of edge computing for this kind of IoT application.



15:00 – 15:40 (GMT-3, Brazil): Invited Talk 3

New Defects in FinFET Technology, their Detection and Reliability Risk

Prof. Victor Champac, INAOE (Mexico)

Session Chair: TBD


Abstract: This talk discusses the behavior and detection of difficult to detect defects in FinFET technology and the reliability risk of possible non-detected defects. FinFET technology incorporates new manufacturing processes, and modern FinFET-based logic cells use multi-fin and multi-finger designs. Thus, due to the 3D nature of FinFET technology,  process complexity, and modern design techniques, new kind of defect topologies may appear. Consequently, it is crucial to analyze these new defect topologies, which need to be considered during test generation. It is shown that classical open defect models, called single open and interconnect open, proposed for CMOS technology are not sufficient in FinFET technology. A FinFET logic cell may be able to implement its intended logic function even in the presence of one or more disconnected fins/fingers, and the delay increase due to the defect is very small. As a consequence, these defects may escape the test process. An important issue is if logic cells presenting such non-detected defects could constitute a risk of failure when the circuit operates in the field. One of the major reliability issues that can affect a defective cell is bias temperature instability (BTI).



16:20 – 17:00 (GMT-3, Brazil): Invited Talk 4

Trustworthy Autonomous Systems: Software-Hardware Error Resilience Using

Hierarchical Algorithmic Checks

Prof. Abhijit Chatterjee, Georgia Institute of Technology (USA)

Session Chair: TBD


Abstract: Trustworthiness and safety play a key role in widespread commercial use of emerging autonomous systems: sensor networks, robots and self-driving cars. In this talk, we focus on self-driving cars and quadcopters.  Due to the complexity of the compute infrastructure, the embedded electronics and electro-mechanical components of such vehicles, unavoidable performance degradation and failures of subsystems as well as external security attacks need to be managed in the field and in real-time to keep traffic flowing freely and without accidents. This, coupled with the need to react to a wide gamut of adversarial driving conditions makes vehicle control with imperfect software and hardware a very challenging problem.  Traditionally failure tolerance has been handled by deploying high degrees of hardware redundancy. This is not cost-effective for  pervasive autonomous systems. In contrast, we propose a resilience methodology based on algorithmic encoding of autonomous system (vehicle) function in a hierarchical manner across all levels of design: from brake-by-wire and steer-by-wire subsystems to high level vehicle control.  In this approach, all vehicle functions such as braking and steering are viewed as algorithms with equivalent electrical and mechanical operations. These algorithms can be encoded for error detection and diagnosis. Once diagnosis is performed, performance correction of the vehicle is initiated with the aid of machine learning based methods.  Test cases and experiments on hardware are presented


Bio: Abhijit Chatterjee is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. Chatterjee has authored over 450 papers in refereed journals and meetings and has 22 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.





October 29th, 2021 (Friday)



10:00 – 10:40 (GMT-3, Brazil): Industry Talk 2

Soft Error becomes a Hard Problem for the Future Electronic Devices

Dr. Sung S. Chung, CTO, QRT Inc. Korea (Korea)

Session Chair: TBD


Abstract: Klaus Schwab characterized the Fourth Industrial Revolution with the mobile internet, cheaper and more powerful sensors, artificial intelligence, and machine learning. Schwab said that these changes, which emerged in the 21st century, are firstly developing at an exponential rate, secondly leading to a paradigm shift by a convergence of various science and technology based on the digital revolution, and thirdly, between countries, between companies, between industries. It is argued that it entails changes in the entire industrial system. The Knowledge Industrial Revolution changed the present industrial society to the knowledge society of the future. It is not a revolution; it's just industrialization. What do these words tell you: super intelligence, hyper-connectivity, EV, green and reusable energy, hyper-speed information exchange, functional safety, and information security. These are all done on chips of the future.

We understand the extrinsic reliability exceeds that of all combined intrinsic reliability; the extrinsic reliability is from "Radiation-Induced Soft Errors." I like to share in my presentation to address these changes with Knowledge Industrialization.

• Changes in Device Test for Safety and Reliability

• Activation and Detection of Soft Errors

• Why Radiation Test cost so much yet provides so little Confidence

• Machine Learning and Intelligent Protection from Single Event Effects.

The presentation raises more questions than answers, but it attempts to guide our attention in the right direction so that we want to be a part of the Knowledge Revolution, which I think we are already engaged in the Revolution.



13:00 – 13:40 (GMT-3, Brazil): Invited Talk 5:

Embedded Wireless Delay Tolerant Networks on Chips for Segmented Architectures

Prof. Pablo Ferreyra, Universidad Nacional de Córdoba (Argentina)

Session Chair: TBD


Abstract: Fault-tolerant systems were initially based on the use of local redundancies. Currently, networks technologies have allowed the emergence of other more distributed alternatives. Indeed, Disruption Tolerant Networks (DTNs) are designed to be robust against all sorts of delays and disruptions. DTNs were initially applied in scenarios with long distances and variable interruptions intervals between their nodes. Wireless Delay Tolerant Networks on Chips (WDTNOCs) have been recently presented as enabling technologies that can inherit some DTNs characteristics while improving embedded systems dependability. This presentation focuses on WDTNOCs under parametric transient fault scenarios. New results demonstrate that, in addition to significant dependability improvements, it is also possible to improve the system's performance and graceful degradation characteristics. Feasibility aspects are also addressed. Finally, as an extremely important application scenario, it is shown how segmented architectures can benefit directly from embedded WDTNOCs.






The LATS2021 Organizing Committee