1ST IEEE LATIN AMERICAN TEST WORKSHOP
Marina Palace Hotel, Rio de Janeiro, Brazil
March 13 - 15, 2000
FINAL PROGRAM
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Sponsored by
IEEE Computer
Test Technology Technical
Society
Council
In Cooperation with
Brazilian Computer Society - SBC
Brazilian National Science Foundation - CNPq
Catholic University - PUCRS, Porto Alegre
Federal University of RGS - UFRGS, Porto Alegre
Federal University of Rio de Janeiro - UFRJ, Rio de Janeiro
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March 12th
IEEE Computer Society Test Technology Educational Program (TTEP)
Full-Day Tutorial, 9:00-16:00
Testing Embedded Core-Based System Chips
Presenters: Yervant Zorian, LogicVision, Inc. - USA
Erik Jan Marinissen, Philips Research Labs. - The Netherlands
March 13th
Opening Address: 7:45-8:00
Session 1 : Self Testing and Self Checking, 8:00-9:15
Moderator: Jan Hlavicka, Czech Technical University
8:00-8:25
Implementing a Self-Checking PROFIBUS Slave
M. R. Krug, M. Lubaszewski, J.M.M. Ferreira, G.R. da Costa Alves
PPGC-UFRGS, Brazil; Faculdade de Engenharia da Universidade do Porto, Portugal
8:25-8:50
Self Test Built-in Plan for Data-Path Functional Units
J. A. Quilici Gonzalez, J. R. de A. Amazonas, M. Strum, W.J. Chau
Laboratório de Microeletrônica da EPUSP, Brazil; Laboratório de Comunicações e Sinais da EPUSP, Brazil
8:50-9:15
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing
F. G. de Lima, E. D'Avila, M. Moraes, M. Lubaszewski, R. Reis
Universidade Federal do Rio Grande do Sul, Brazil
9:15-9:35 Coffee Break
Session 2 : Fault Tolerance, 9:35-10:50
Moderator: Ingrid Jansch Porto, Federal University of RGS
9:35-10:00
FTRT_OS - A Fault-Tolerant Operating System for Real-Time Applications: An Experience with
Digital Signal Processor (DSP) Architecture
H. S. Castro, P. R.C. de Araujo, G. C. Barroso
Universidade Federal do Ceará, Brazil
10:00-10:25
Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation
F. Vargas, A. Amory, R. Velazco
Catholic University - PUCRS, Brazil; TIMA-INPG, France
10:25-10:50
Hardening the Software with Respect to Transient Errors: a Method and Experimental Results
P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza, M. Violante
INPG-Laboratoire TIMA, France; Politecnico di Torino, Italy
Session 3 : Defect Oriented Test, 10:50-12:05
Moderator: Michel Renovell, LIRMM
10:50-11:15
Defect Oriented Testing of an ECL/CMOS Level Converter Circuit
M-H. P. Chen, A. Ivanov, S. Tabatabaei
University of British Columbia-Canada
11:15-11:40
Detectability Dependency on Test Generation Process for Interconnection Opens
A. Zenteno, Victor H.Champac, J. Figueras
INAOE, Mexico; University of Catalonia, Spain
11:40-12:05
Transient Current Monitoring Using a Current-to-Frequency Converter
P. Picos, J. Colom, M. Roca, E. Isern, J. Segura, O. Calvo, E. Garcia Moreno
University of the Balearic Island, Spain; Universidad Nacional de la Plata, Argentina
12:05-14:05 Lunch
Session 4 : ATPG and Testability, 14:05-15:20
Moderator: Yervant Zorian, LogicVision, Inc
14:05-14:30
Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-
Chip
M. B. Santos, J. P. Teixeira
IST/INESC, Portugal
14:30-14:55
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an
Experiment with a PowerPC Microprocessor
J. Bhadra, M. S. Abadir, J. Abraham
University of Texas at Austin, USA; Motorola Inc., USA
14:55-15:20
Testability of Circuits Derived from Lattice Diagrams
R. Drechsler, W. Gunther, B. Becker
Albert Ludwigs University, Germany
15:20-15:40 Coffee Break
Session 5: Analog Testing I, 15:40-16:30
Moderator: Jose Luis Huertas, U. of Sevilla
15:40-16:05
Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order
Filter Approximations using the Transient Response Analysis Method
J. V. Calvano, V. Castro Alves, M. S. Lubaszewski
Brazilian Navy Research Institute, Brazil; Federal University of Rio de Janeiro, Brazil; Federal University of
Rio Grande do Sul, Brazil
16:05-16:30
On the Temperature Dependencies of Analog BIST
L. Carro, M. Renovell, E. Cota, M. Lubaszewski, Y. Bertrand, F. Azais
UFRGS, Brazil; LIRMM, France
16:30-17:30
Invited Talk:
Software-Based Fault Injection Mechanisms
E. Martins, Unicamp - Brazil
18:00-18:45
Open Session: IEEE LA-TTTC Group Meeting
Coordinator: F. Vargas, PUCRS - Brazil
March 14th
Session 6 : BIST Approaches, 8:00-09:15
Moderator: Magdy Abadir, Motorola - USA
8:00-8:25
Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths
M. Psarakis, N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian
II&T NCSR "Demokritos", Greece; University of Piraeus, Greece; University of Athens, Greece; LogicVision,
USA
8:25-8:50
On the Study of a New BIST Technique Using Reseeding of Linear Feedback Shift Register to
Accelerate the Test
S. Caceres, J. M. Ruiz, J. A. Dominguez, S. de Pablo
Universidad de Valladolid, Spain
8:50-9:15
Cost/Quality Trade-Off in Synthesis for BIST
P. Bukovjan, L. Ducerf, M. Marzouki
ON Semiconductor, Czech Republics; LIP6/ASIM Laboratory, France
9:15-9:35 Coffee Break
Session 7 : Mixed Signal Testing, 9:35-10:50
Moderator: Andre Ivanov, U. of British Columbia
9:35-10:00
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital
Converters
S. Bernard, F. Azais, Y Bertrand, M. Renovell
Université de Montpellier, France
10:00-10:25
Alternative DFT Strategies for High-Speed Pipelined Data Converters
E. Peralias, A. Rueda, J. L. Huertas
IMSE - CNM, Spain
10:25-10:50
Block-Based Test Integration for Analog Integrated Circuits
S. Ozev, A. Orailoglu
University of California, USA
Session 8 : Fault Tolerance and BIST, 10:50-12:05
Moderator: Eliane Martins, Unicamp
10:50-11:15
Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults
E. F. Cota, L. Carro, M. Lubaszewski, R. Velazco, S. Rezgui
UFRGS, Brazil; TIMA Laboratory, France
11:15-11:40
Fail-Safe and Test for Electronic Control Systems Using PLCs
J. Marcos, E. Mandado, C. Peñalver, A. Lago
University of Vigo, Spain
11:40-12:05
Merging BIST and Configurable Computing Technology to Improve Availability in Space
Applications
E. Bezerra, F. Vargas, M. P. Gough
University of Sussex, England; Catholic University - PUCRS, Brazil
12:05-14:05 Lunch
Session 9 : Diagnosis, 14:05-15:20
Moderator: Alex Orailoglu, U. of California - San Diego
14:05-14:30
A Synchronous Testing Strategy for Hierarchical Adaptive Distributed System-Level Diagnosis
A. Brawerman, E. P. Duarte Jr.
Federal University of Parana, Brazil
14:30-14:55
Reliable Diagnosis of Grid-Connected Systems
A. Caruso, S. Chessa, P. Maestrini, P. Santi
Istituto di Elaborazione dell'Informazione del CNR, Italy; University of Pisa, Italy
14:55-15:20
A Token-Based Testing Strategy for Non-Broadcast Network Diagnosis
J. I. Siqueira, E. Fabris, E. P. Duarte Jr.
Federal University of Paraná, Brazil
15:20-15:40 Coffee Break
Session 10 : Yield and Process Characterization, 15:40-16:30
Moderator: Ricardo Reis, Federal University of RGS
15:40-16:05
Electronic Process Limited Yield
G.W. Maier, S. Smith
IBM Corporation and Knights Technologies, USA
16:05-16:30
Determination of Silicon Film Thickness in SOI Capacitors
V. Sonnerberg, J. A. Martino
LSI/PEE/USP, Brazil; FATEC/SP/CEETEPS, Brazil
16:30-18:30
Special Session 1: Test Technology Industrial Experiences in Brazil
Panelists:
CPqD/TELEBRAS - Center for Telecommunications Research and Development
(www.cpqd.com.br)
CTI - Center for Informatics Technology (www.cti.br)
Moderator: Fabian Vargas, PUCRS
Co-organized with IEEE Design & Test of Computers
21:00-23:00
Banquet - Welcome Reception
March 15th
Session 11 : Analog Testing II, 8:00-9:15
Moderator: Florence Azais, Université de Montpellier II
8:00-8:25
The Use of Macromodels on Op-Amp Circuits Fault Modeling
J. V. Calvano, V. Castro Alves, M. S. Lubaszewski
Brazilian Navy Research Institute, Brazil; Federal University of Rio de Janeiro, Brazil; Federal University of
Rio Grande do Sul, Brazil
8:25-8:50
On-Line BIST for Testing Analog Circuits
J. Velasco-Medina, I. Rayane, M. Nicolaidis
INPG-TIMA, France
8:50-9:15
RSM and Simplex Optimization for Parametric Fault Diagnosis of Analog Integrated Circuits
J. L. Vazquez, G. Espinosa
INAOE, Mexico; Universidad de las Americas, Mexico
9:15-9:35 Coffee Break
Session 12 : DFT Techniques, 9:35-10:50
Moderator: Marius Strum, Sao Paulo University
9:35-10:00
Test Configuration Generation for FPGA Logic Cells
M. Renovell, J.M. Portal, J. Figueras, Y. Zorian
LIRMM-UM2, France; UPC, Spain; LogicVision Inc., USA
10:00-10:25
Using Reconfigurability Features to Break Down Test Costs: a Case Study
L. Carro, L. Agostini, R. Pacheco, M. Lubaszewski
CPGCC/DELET/UFRGS-Brazil
10:25-10:50
The Test-Cycle Minimization in Parameterized Bus-Oriented Datapath Designs
V. A. Zivkovic, R. J. W. T. Tangelder, H.G. Kerkhoff
University of Twente, The Netherlands
Session 13 : Software Testing and System Modeling, 10:50-12:05
Moderator: Meryem Marzouki, LIP6 Lab
10:50-11:15
Path Selection Strategies in the Context of Software Testing Criteria
L. M. Peres, S. R. Vergilio, M. Jino, J. Maldonado
UNIOESTE, Brazil; UFPR, Brazil; UNICAMP, Brazil; USP, Brazil
11:15-11:40
Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing
S. R. Vergilio, J. C. Maldonado, M. Jino
UFPR, Brazil; ICMSC/USP, Brazil; DCA/FEEC/UNICAMP, Brazil
11:40-12:05
Codesign System Modeling for Performance Analysis
L. M. Mourelle, N. Nedjah
Universidade do Estado do Rio de Janeiro, Brazil
12:05-14:05 Lunch
Session14: Diagnosis and Testability Analysis, 14:05-15:20
Moderator: Raoul Velazco, TIMA-INPG
14:05-14:30
Design Optimization Based on Diagnosis Techniques
A. Veneris, M. S. Abadir, I. N. Hajj
University of Toronto, Canada; Motorola, USA; University of Illinois, USA
14:30-14:55
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test
Y. Makris, A. Orailoglu
University of California, USA
14:55-15:20
Formal Approach to the RTL Testability Analysis
Z. Kotasek, R. Ruzicka, J. Hlavicka
Brno University of Technology, Czech Republic; Czech Technical University, Czech Republic
15:20-15:40 Coffee Break
Session 15 : Process Characterization, 15:40-16:55
Moderator: Oscar Calvo, Universidad Nacional de la Plata - UNLP
15:40-16:05
A New Method to Extract the Silicon Film Thickness of Enhancement Mode Fully Depleted SOI
NMOSFETs
A. S. Nicolett, J. A. Martino, E. Simoen, C. Claeys
LSI/PEE/USP, Brazil; FATEC, Brazil; IMEC, Belgium; KU Leuven, Belgium
16:05-16:30
Analysis of the Leakage Drain Current in Accumulation-Mode SOI pMOSFETS Operating up to 300 C
M. Bellodi, J. A. Martino
Escola Politécnica da Universidade de São Paulo, Brazil
16:30-16:55
Effective Channel Length and Series Resistance Extraction Error Induced by the Substrate in
Enhancement-Mode SOI nMOSFETs
M. A. Pavanello, A. S. Nicolett, J. A. Martino
Escola Politécnica da Universidade de São Paulo, Brazil; FATEC-SP, Brazil; FEI-FCA São Bernardo do
Campo, Brazil
16:55-17:45
Invited Talk:
Economics of Testing
Magdy Abadir, Motorola - USA
Closing Remarks: 17:45-18:00
